1. Field of the Invention
The present invention generally relates to mixed voltage integrated circuits utilizing plural voltage power supplies and, more particularly, to high density integrated circuits involving hybrid technologies or having logic level conversion circuitry and in which voltages applied to circuit elements therein may be limited.
2. Description of the Prior Art
Economies of manufacture and improved levels of performance generally result from increased integration density in semiconductor integrated circuits. Increasing the number of devices produced on a wafer or a chip diced therefrom reduces the cost of each device so formed by complex and costly manufacturing processes. Increased uniformity of the devices and improved manufacturing yield generally result, as well. Reduced signal propagation time and increased noise immunity result from reduced connection capacitance as devices on a chip are formed in greater proximity. Reduced circuit element (e.g. transistor) dimensions also generally increase frequency response and reduce switching time by reducing parasitic capacitances.
Field effect transistors, particularly of the metal-oxide-semiconductor (MOS) type, have become favored in recent years due to comparative ease and economy of manufacture, increased uniformity of circuit performance and higher manufacturing yield relative to bipolar transistors for many applications. However, field effect transistors are generally formed laterally with the conduction channel parallel to the substrate surface and high integration density therefore implies that conduction channels must be very short. Short conduction channels, in turn, limit the voltage range over which they will optimally perform without exhibiting short channel effects, increased "off" current and the like.
Additionally, reducing lateral dimensions of field effect transistors to smaller sizes generally requires reduction of the thickness of the gate insulator over the conduction channel to maintain or improve high frequency performance and switching speed. The reduced thickness of gate insulator also limits the voltage relative to the substrate or well which can be applied thereto without breakdown. In view of the digital environment in which such high density integrated circuits are generally applied, it is customary to design the conduction channel and the gate oxide to withstand approximately the same voltage. Since providing for a higher voltage to be withstood (e.g. to selectively form a thicker oxide at some locations) at points in a design where higher voltages might be applied increases manufacturing process complexity, this design criterion essentially limits the voltage which can be applied across any element on the chip.
At the present state of the art, the nominal voltage level which a field effect transistor must withstand without compromising reliability has been reduced to about 1.8 volts. For comparison, while voltage reductions are required for other technologies when integrated at densities which the level of skill in the lithographic art will support, many circuits and processors currently use a logic voltage level of about 3.3 volts, particularly for communication over connections which may be more susceptible to noise.
Accordingly, current integrated circuit designs often include voltage level conversion circuitry, sometimes referred to as level shifters, at the inputs and outputs (I/O's) thereof. Such level shifters of many designs are known but inclusion of some transistors which must be switched cannot generally be avoided. Thus, the level shifters of a chip of current complexity may involve the precisely simultaneous switching of thousands of transistors which presents a source of high frequency noise at the high voltage supply of the chip, sometimes referred to as a "bounce", which may be propagated through the low voltage source to the logic circuitry of the chip unless filtering is provided.
While noise increases with switching speed, particularly at the higher voltage, noise is not as severe at the lower voltage due to the 10-100 nf of decoupling capacitance of the chip since transistors are generally formed in impurity wells referenced to the low voltage supply while the substrate is referenced to ground. Also, as a practical matter, much less simultaneous switching occurs at the lower voltage in the logic circuitry of the chip.
Filtering to reduce switching noise would be most efficiently done by decoupling the high voltage supply to ground through a capacitive network of parallel connected capacitors. The most desirable type of decoupling capacitor is a thin oxide capacitor which has an oxide thickness similar to the gate insulator of the field effect transistors on the chip. Such capacitors have a high capacitance per unit area and are thus compatible with high integration density. However, the thin oxide which provides the high capacitance will have poor reliability if the high voltage supply is applied across it. Therefore, the higher voltage is generally capacitively connected to the lower voltage supply in series with the well capacitance in order to reduce the voltage which must be withstood by the capacitor dielectric which is preferably formed in the same process as the gate insulators of the transistors.
Such a configuration, however, imposes conflicting design considerations and requires a trade-off between several design factors apart from increased process complexity for forming a capacitor capable of withstanding the higher voltage. Specifically, the ratio of the capacitance value of the capacitor coupling the high voltage supply to the low voltage supply should be small to prevent coupling of the "bounce" to the low voltage supply. On the other hand, if the capacitance of the capacitor coupling the high voltage supply to the low voltage supply is small, the high voltage supply becomes more noisy and the noise may be coupled to low voltage circuitry by other mechanisms for which the filtering of the well capacitance may be less effective.
For example, if the capacitance ratio between high voltage to low voltage and low voltage and ground is kept at 1:3 to maintain low noise coupling from the high voltage supply to the low voltage supply, three times the area of the capacitor between the high and low voltage supplies will be required for the capacitance between low voltage and ground. Given that a significant value of capacitance between the high and low voltage supplies will be needed to limit noise on the high voltage supply, the corresponding value of capacitance between the low voltage supply and ground may easily exceed the available capacitance of the dopant/impurity well and require additional capacitance to be provided if, in fact, space is available on the chip to do so. Accordingly, there is a relatively small "window" of capacitance values which will yield acceptable performance and that "window" will diminish with increase of switching speed and the number of I/O circuits which are provided on the chip (which usually increases with integration density and chip functionality).
In this regard, it should be noted that the capacitance per unit area of a thin oxide capacitor is approximately ten times that of an impurity well. Therefore, if a given value of capacitance coupling the high voltage supply to the low voltage supply to avoid excess noise of the high voltage supply and a given ratio of that capacitance to the impurity well capacitance must be maintained to limit noise on the low voltage supply, it can be appreciated that the area required to couple the noise on the low voltage supply to ground must be ten times the ratio larger than the area of the thin film capacitor unless the impurity well capacitance can be augmented in some manner. Such augmentation cannot generally be done without reserving area on the chip which would otherwise be useable for other structures, thus limiting the amount of, for example, logic or storage which can be fabricated on the chip.
A further practical complication may also arise from the fact that increased chip functionality (e.g. more complicated logic, more types of logic functions, and the like) available by virtue of increased integration density increases the number of I/O pads or other types of connections to the chip which must be provided. It is not uncommon at the present state of the art for the entire surface of a chip to be populated with I/O pads, particularly since numerous pads are often connected in parallel to provide power connections to the chip. The area of I/O pads cannot be easily decreased since each I/O pad must accommodate a physical connection structure such as a pin to be attached thereto, preferably by brazing. The total area of the I/O pads and their layout is in direct conflict with the formation of relatively large-valued decoupling capacitors, particularly of the thin oxide type which preferably extend across a portion of the surface of the chip.